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Workshop/ Tutorial

Morning: More-Moore


Chung-Hsun Lin (Senior Director, Intel, USA)    

Title: Advanced CMOS Transistor Scaling Towards 1nm Node and Beyond

As FinFET scaling comes to an end in 3nm node, there are several innovative device and standard cell architectures considered for 2nm node and beyond: from gate-all-around (GAA) transistor, backside power delivery, complementary FET (CFET), to atomic channel FET with 2D materials. The GAA transistor is the most pragmatic architecture in the near term to enable incremental contact-poly pitch and gate length scaling because of its limited perturbation to a conventional FinFET process integration and design flows. Backside power delivery and CFET (3D stacking) technology brings additional cell level area scaling benefit as well as heterogeneous integration benefit for high mobility channel enablement.  2D material FET provides the ultimate gate length scaling with high mobility channel capability. In this short course, we will focus on technology and device design value proposition for these innovations with the corresponding engineering opportunities and challenges for high volume manufacturing.

Steven Hung (Senior Director/Scientist, Applied Materials, USA)    

Title: Innovations of Material and Process Engineering in the Angstrom Era for Advanced
         CMOS Logic Technology

The relentless pursuit of Moore's Law scaling has led to the emergence of the
Angstrom era. 3D device architectures, such as gate-all-around (GAA) transistors,
provide enhanced control and scalability. Process advancements include EUV
lithography, atomic layer deposition & etching, and directed self-assembly deposition enabling precise control at the atomic scale. These innovations overcome fundamental limitations, delivering significant improvements in power, performance, area & cost (PPAC) as well as facilitating continuous advancement in CMOS technology for next generation computing applications. This tutorial explores the pivotal role of material and process advancements in the Angstrom era pushing the boundaries of advanced logic CMOS technology.
Firstly, it delves into the current state-of-art GAA nanosheet (NS) technology and the key challenges. Various process and device solutions to extend GAA
NS for upcoming technology nodes will be discussed. The synergistic effects of
integrating material and process innovations leading to enhanced device performance, reduced power consumption and area scaling in GAA NS technology will be addressed.
Furthermore, this course will examine the 3D CFET/Stacked-FET architecture and its fabrication options. It will also highlight the recent progress of monolithic-CFET (m-CFET) in the industry. Lastly, key unit process bottlenecks will be illustrated in a generic m-CFET flow.


Philippe Blaise (Silvaco, USA )   

Title: Atomistic Simulation, a Key Enabler for Next-Generation TCAD Tools

The atomistic simulation tools are very promising, bringing advanced functionalities with unprecedented predictive power. Nevertheless, they are not easy to use and qualify which slows down their adoption by the TCAD community. This presentation will illustrate the full potential of atomistic simulation on several examples, with a special focus on quantum transport for small structures and 2D materials. We will also explore the various links between quantum chemistry, quantum transport and conventional TCAD. The ultimate goal is to embed the atomistic simulation in the prototyping effort of advanced devices. We hope to deliver a guide for non-specialists in quantum physics to use such tools in their daily work.

Afternoon: More-than-Moore


Ilon Joseph ( Acting Group Leader, LLNL, USA )     

Title: Quantum Computing for Fusion Energy Science Applications


Quantum computing promises to deliver large gains in computational power that can potentially benefit a number of Fusion Energy Science (FES) application areas. We will review our recent efforts [1] to develop and extend quantum algorithms to perform both classical and quantum FES-relevant calculations, as well as to perform calculations on present-day quantum hardware platforms. We have developed and explored quantum algorithms that can compute nonlinear and non-Hamiltonian dynamics by simulating the Koopman-von Neumann and Liouville equations; perform eigenvalue estimation for generalized eigenvalue problems common in plasma physics and MHD theory; simulate nonlinear wave-wave interactions; and explore the chaotic dynamics of both quantum and classical systems.  We have implemented toy models of these algorithms on state-of-the-art quantum computing architectures to test the fidelity of emerging quantum hardware capabilities including Grover’s search, nonlinear three-wave interactions, and the chaotic dynamics of the quantum sawtooth map, a simple model for wave-particle interactions. The fidelity of the experimental results match noise models that include decay and dephasing processes and highlights key differences between state-of-the-art approaches to quantum computing hardware platforms.


Yuhao Zhang (Assistant Professor, CPES, Virginia Tech, USA)

Title: TCAD Simulation in Power Semiconductors and Power Electronic


Power electronics technologies provide electrical energy conversion using semiconductor devices and passive components. The global power semiconductor market has reached US$40 billion and is rapidly expanding, driven by applications like electric vehicles, data centers, consumer electronics, electric grids, and renewable energy processing.  TCAD simulation is critical for the design, packaging, circuit application, and reliability studies of power devices. As the operation of power devices involves the concurrence of high voltage and high current in submicron-second, large-signal switching transients, their TCAD simulations, particularly for devices based on wide-bandgap (WBG) and ultra-wide bandgap (UWBG) semiconductors, face unique challenges and opportunities. This talk will introduce such challenges and opportunities using examples of WBG and UWBG device simulation in the following topics: 1) high-field carrier transport and breakdown simulation, 2) device-package electro-thermal simulation, 3) device-circuit mixed-mode simulation, and 4) stability, reliability, and robustness simulation.


Norman Chang (Ansys Fellow, Ansys, USA )     

Title: Challenges and Solutions on Physical Integrity of 3D Heterogeneous Integration System


Emerging 3DIC systems enabled by advanced packaging techniques promise high integration density and manufacturing yield. However, due to the complexity of integrating multiple, heterogeneous chiplets into a chip-package-system, multi-die applications that are built with 3DICs are challenged by multiphysics issues on power, signal, thermal, structural, and timing integrity. In this tutorial, a comprehensive EDA platform will be illustrated that uses 3Dblox™ to enable 3DIC multiphysics simulation at all multi-die design stages - from early physical architecture planning to final design signoff. This platform enabled by a novel methodology for system technology co-optimization will also be reviewed by using Generative AI (GenAI) and ML-assisted approaches. This allows the platform to address a range of multiphysics design and optimization challenges. Successful example multiphysics applications will be described.

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